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GigaDevice Semiconductor GD32F3x0 - DAC Workflow; DAC Noise Wave; Figure 12-2. DAC LFSR Algorithm

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GD32F3x0 User Manual
196
DTSEL[2:0]
Trigger Source
Trigger Type
3b’110
EXTI9
3b’111
SWTRIG
Software trigger
The TIMERx_TRGO signals are generated from the timers, while the software trigger can be
generated by setting the SWTR bit in the DAC_SWT register.
12.3.5. DAC workflow
If the external trigger enabled by setting the DTEN bit in DAC_CTL register, the DAC holding
data is transferred to the DAC output data (DAC_DO) register when the selected trigger
events. When the external trigger is disabled, the transfer is performed automatically.
When the DAC holding data (DAC_DH) is loaded into the DAC_DO register, after the time
t
SETTLING
, the analog output is valid, and the value of t
SETTLING
is related to the power supply
voltage and the analog output load.
12.3.6. DAC noise wave
There are two methods of adding noise wave to the DAC output data: LFSR noise wave
mode and triangle wave mode. The noise wave mode can be selected by the DWM bits in
the DAC_CTL register. The amplitude of the noise can be configured by the DAC noise wave
bit width (DWBW) bits in the DAC_CTL register.
LFSR noise wave mode: there is a Linear Feedback Shift Register (LFSR) in the DAC
control logic, it controls the LFSR noise signal which is added to the DACx_DH value. When
the configured DAC noise wave bit width is less than 12, the noise signal equals to the LSB
DWBWx bits of the LFSR register, while the MSB bits are masked.
Figure 12-2. DAC LFSR algorithm
9
7
8
6 5 4 3 2 1
11
10
0
X
6
X
0
X
4
X
XOR
X
12
NOR
12
Triangle noise mode: in this mode, a triangle signal is added to the DACx_DH value. The

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