GigaDevice Semiconductor GD32F3x0 - DD DDA Power Domain; Figure 3-2. Waveform of the por; PDR

GD32F3x0 User Manual
59
lines to achieve the RTC timer wakeup event. After entering the power saving mode for a
certain amount of time, the RTC alarm will wake up the device when the time match event
occurs. The details of the RTC configuration and operation will be described in the Real-time
clock (RTC) .
When the Backup domain is supplied by V
DD
(V
BAK
pin is connected to V
DD
), the following
functions are available:
 PC13 can be used as GPIO or RTC function pin described in the Real-time clock
(RTC) .
 PC14 and PC15 can be used as either GPIO or LXTAL Crystal oscillator pins.
When the Backup domain is supplied by V
BAT
(V
BAK
pin is connected to V
BAT
), the following
functions are available:
 PC13 can be used as RTC function pin described in the Real-time clock (RTC).
 PC14 and PC15 can be used as LXTAL Crystal oscillator pins only.
Note: Since PC13, PC14, PC15 are supplied through the Power Switch, which can only be
obtained by a small current, the speed of GPIOs PC13 to PC15 should not exceed 2MHz
when they are in output mode (maximum load: 30pF).
3.3.2. V
DD
/ V
DDA
power domain
V
DD
/ V
DDA
domain includes two parts: V
DD
domain and V
DDA
domain. V
DD
domain includes
HXTAL (high speed crystal oscillator), LDO (voltage regulator), POR / PDR (power on / down
reset), FWDGT (free watchdog timer), all pads except PC13 / PC14 / PC15, etc. V
DDA
domain includes ADC / DAC (AD / DA converter), IRC8M (internal 8MHz RC oscillator),
IRC48M (internal 48MHz RC oscillator at 48MHz frequency), IRC28M (internal 28MHz RC
oscillator at 28MHz frequency), IRC40K (internal 40KHz RC oscillator), PLLs (phase locking
loop), LVD (low voltage detector), etc.
V
DD
domain
The LDO, which is implemented to supply power for the 1.2V domain, is always enabled
after reset. It can be configured to operate in three different status, including in the Sleep
mode (full power on), in the Deep-sleep mode (on or low power), and in the Standby mode
(power off).
The POR / PDR circuit is implemented to detect V
DD
/ V
DDA
and generate the power reset
signal which resets the whole chip except the Backup domain when the supply voltage is
lower than the specified threshold. Figure 3-2. Waveform of the POR / PDR shows the
relationship between the supply voltage and the power reset signal. V
POR
, which typical value
is 2.4V, indicates the threshold of power on reset, while V
PDR
, which typical value is 1.8V,
means the threshold of power down reset. The hysteresis voltage (V
hyst
) is around 600mV.
Note: V
DDA
monitor function detected by the PDR circuit can be disabled by reset
VDDA_VISOR bit in option byte register OB_USER, to reduce power consumption when
users are sure that the V
DDA
is higher than or equal to V
DD
.