GigaDevice Semiconductor GD32F3x0 - Register Definition

GD32F3x0 User Manual
146
8.4. Register definition
CRC base address: 0x4002 3000
8.4.1. Data register (CRC_DATA)
Address offset: 0x00
Reset value: 0xFFFF FFFF
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DATA[31:16]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[15:0]
rw
Bits
Fields
Descriptions
31:0
DATA[31:0]
CRC calculation result bits
Software write and read.
This register is used to calculate new data, and the register can be written the new
data directly. Write value cannot be read because the read value is the previous
CRC calculation result.
8.4.2. Free data register (CRC_FDATA)
Address offset: 0x04
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
FDATA[7:0]
rw
Bits
Fields
Descriptions
31:8
Reserved
keep at reset value
7:0
FDATA[7:0]
Free Data Register bits
Software write and read.