GigaDevice Semiconductor GD32F3x0 - Alarm 0 Sub Second Register (RTC_ALRM0 SS)

GD32F3x0 User Manual
247
4
TP1EG
Tamper 1 event trigger edge
If tamper detection is in edge mode (FLT = 0):
0: Rising edge triggers a tamper detection event
1: Falling edge triggers a tamper detection event
If tamper detection is in level mode(FLT ≠ 0):
0: Low level triggers a tamper detection event
1: High level triggers a tamper detection event
3
TP1EN
Tamper 1 detection enable
0: Disable tamper 1 detection function
1: Enable tamper 1 detection function
Note: It’s strongly recommended that reset the TP1EN before change the tamper
configuration.
2
TPIE
Tamper detection interrupt enable
0: Disable tamper interrupt
1: Enable tamper interrupt
1
TP0EG
Tamper 0 event trigger edge
If tamper detection is in edge mode (FLT = 0):
0: Rising edge triggers a tamper detection event
1: Falling edge triggers a tamper detection event
If tamper detection is in level mode (FLT ≠ 0):
0: Low level triggers a tamper detection event
1: High level triggers a tamper detection event
0
TP0EN
Tamper 0 detection enable
0: Disable tamper 0 detection function
1: Enable tamper 0 detection function
Note: It’s strongly recommended that reset the TP0EN before change the tamper
configuration.
15.4.15. Alarm 0 sub second register (RTC_ALRM0SS)
Address offset: 0x44
Backup domain reset: 0x0000 0000
System reset: no effect
This register is write protected and can only be wrote when ALRM0EN=0 or INITM=1.
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
MSKSSC[3:0]
Reserved
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SSC[14:0]
rw