GigaDevice Semiconductor GD32F3x0 - Channel X Counter Register (Dma_Chxcnt)

GD32F3x0 User Manual
161
4
DIR
Transfer direction
Software set and cleared
0: Read from peripheral and write to memory
1: Read from memory and write to peripheral
This bit can not be written when CHEN is ‘1’.
3
ERRIE
Enable bit for channel error interrupt
Software set and cleared
0: Disable the channel error interrupt
1: Enable the channel error interrupt
2
HTFIE
Enable bit for channel half transfer finish interrupt
Software set and cleared
0:Disable channel half transfer finish interrupt
1:Enable channel half transfer finish interrupt
1
FTFIE
Enable bit for channel full transfer finish interrupt
Software set and cleared
0:Disable channel full transfer finish interrupt
1:Enable channel full transfer finish interrupt
0
CHEN
Channel enable
Software set and cleared
0:Disable channel
1:Enable channel
9.5.4. Channel x counter register (DMA_CHxCNT)
x = 0...6, where x is a channel number
Address offset: 0x0C + 0x14 × x
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT[15:0]
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
CNT[15:0]
Transfer counter
These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’.
This register indicates how many transfers remain. Once the channel is enabled, it