1.3.1. Bit-banding
In order to reduce the time of read-modify-write operations, the Cortex
®
-M4 processor
provides a bit-banding function to perform a single atomic bit operation. The memory map
includes two bit-band regions. These occupy the SRAM and Peripherals respectively. These
bit-band regions map each word in an alias region of memory to a bit in a bit-band region of
memory.
A mapping formula shows how to reference each word in the alias region to a corresponding
bit, or target bit, in the bit-band region. The mapping formula is:
bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) (1-1)
where:
bit_word_addr is the address of the word in the alias memory region that maps to the
targeted bit.
bit_band_base is the starting address of the alias region.
byte_offset is the number of the byte in the bit-band region that contains the targeted bit.
bit_number is the bit position (0-7) of the targeted bit.
For example, to access bit 7 of address 0x2000 0200, the bit-band alias is:
bit_word_addr = 0x2200 0000 + (0x200 * 32) + (7 * 4) = 0x2200 401C (1-2)
Writing to address 0x2200 401C will cause bit 7 of address 0x2000 0200 change while a
read to address 0x2200 401C will return 0x01 or 0x00 according to the value of bit 7 at the
SRAM address 0x2000 0200.
1.3.2. On-chip SRAM memory
The GD32F3x0 series contain up to 16KB of on-chip SRAM which starts at the address
0x2000 0000. It supports byte, half-word (16 bits), and word (32 bits) access. In order to
increase memory robustness, parity check is supported. The user can enable the parity
check function using the bit SRAM_PARITY_CHECK in the user option byte (refer to
Chapter 2.3.9 Option byte description). When enabled, an NMI is generated if the parity
check fails. The SRAM parity check error flag is implemented in the system configuration
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