GigaDevice Semiconductor GD32F3x0 - Control Register (CRC_CTL); Initialization Data Register (CRC_IDATA)

GD32F3x0 User Manual
147
These bits are unrelated with CRC calculation. This byte can be used for any goals
by any other peripheral. The CRC_CTL register will generate no effect to the byte.
8.4.3. Control register (CRC_CTL)
Address offset: 0x08
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
REV_O
REV_I[1:0]
PS[1:0]
Reserved
RST
rw
rw
rw
rs
Bits
Fields
Descriptions
31:8
Reserved
Keep at reset value
7
REV_O
Reverse output data value in bit order
0: Not bit reversed for output data
1: Bit reversed for output data
6:5
REV_I[1:0]
Reverse type for input data
0: Dot not use reverse for input data
1: Reverse input data with every 8-bit length
2: Reverse input data with every 16-bit length
3: Reverse input data with whole 32-bit length
4:3
PS[1:0]
Size of polynomial
0: 32 bit
1: 16 bit (POLY[15:0] is used for calculation)
2: 8 bit(POLY[7:0] is used for calculation)
3: 7 bit(POLY[6:0] is used for calculation)
2:1
Reserved
Keep at reset value
0
RST
This bit can reset the CRC_DATA register to the value in CRC_IDATA then
automatically cleared itself to 0 by hardware. This bit will generate no effect to
CRC_FDATA.
Software write and read.
8.4.4. Initialization data register (CRC_IDATA)
Address offset: 0x10