GigaDevice Semiconductor GD32F3x0 - Write Protection Key Register (RTC_WPK); Sub Second Register (RTC_SS); Shift Function Control Register (RTC_SHIFTCTL)

GD32F3x0 User Manual
241
15.4.7. Write protection key register (RTC_WPK)
Address offset: 0x24
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
WPK[7:0]
w
Bits
Fields
Descriptions
31:8
Reserved
Must be kept at reset value.
7:0
WPK[7:0]
Key for write protection
15.4.8. Sub second register (RTC_SS)
Address offset: 0x28
System reset value: 0x0000 0000 when BPSHAD = 0.
Not affected when BPSHAD = 1.
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSC[15:0]
r
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
SSC[15:0]
Sub second value
This value is the counter value of synchronous prescaler. Second fraction value is
calculated by the below formula:
Second fraction = ( FACTOR_S - SSC ) / ( FACTOR_S + 1 )
15.4.9. Shift function control register (RTC_SHIFTCTL)
Address offset: 0x2C
System reset: not effect
Backup Reset value: 0x0000 0000
This register is writing protected and can only be wrote when SOPF = 0.
This register has to be accessed by word(32-bit).