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GigaDevice Semiconductor GD32F3x0 - Function Overview

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GD32F3x0 User Manual
172
11.4. Function overview
Figure 11-1. ADC module block diagram
ADC_IN0
ADC_IN1
· · ·
ADC_IN15
GPIO
Channel selector
VBAT/2
VREFINT
VDDA
VSSA
6~12-bit
Routine data registers
(16 bits)
Routine
channels
Channel Mangement
Trig select
EXTI_11
TIMER
0_CH0
TIMER
0_CH1
TIMER
0_CH2
TIMER
1_CH1
TIMER
2_TRGO
TIMER
14_CH0
Analog
watchdog
A
P
B
B
U
S
EOC
watchdog
event
Interrupt
generator
ADC
Interrupt
SWRCST
SAR ADC
CLB
self calibration
DRES[1:0]
12, 10, 8, 6 bits
OVSS[3:0]
OVSR[2:0]
OVSEN
TOVS
VSENSE
DMA request
Over
sampler
11.4.1. Foreground calibration function
During the foreground calibration procedure, the ADC calculates a calibration factor which is
internally applied to the ADC until the next ADC power-off. The application can not use the
ADC until the calibration is completed. The calibration should be performed before starting A
/ D conversion. The calibration is initiated by setting the CLB bit to 1. The CLB bit stays at 1
during the calibration sequence. Then it is then cleared by hardware as soon as the
calibration is completed.
When the ADC operating conditions change (such as supply power voltage V
DDA
,
temperature and so on), it is recommended to re-run a calibration cycle.
The internal analog calibration can be reset by setting the RSTCLB bit in ADC_CTL1
register.
Calibration software procedure:
1. Ensure that ADCON=1.
2. Delay 14 CK_ADC to wait for ADC stability.
3. Set RSTCLB (optional).
4. Set CLB=1.
5. Wait for CLB =0.

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