GD32F3x0 User Manual
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Note: The Information Block stores the bootloader - this block cannot be programmed or
erased by user.
2.3.2. Read operations
The flash can be addressed directly as a common memory space. Any instruction fetch and
the data access from the flash are through the IBUS or DBUS from the CPU.
2.3.3. Unlock the FMC_CTL register
After reset, the FMC_CTL register is not accessible in write mode, except for the OBRLD bit,
which is used for reloading the option byte, and the LK bit in FMC_CTL register is 1. An
unlocking sequence consists of two write operations to the FMC_KEY register can open the
access to the FMC_CTL register. The two write operations are writing 0x45670123 and
0xCDEF89AB to the FMC_KEY register. After the two write operations, the LK bit in
FMC_CTL register is set to 0 by hardware. The software can lock the FMC_CTL again by
setting the LK bit in FMC_CTL register to 1. If there is any wrong operations on the
FMC_KEY register, the LK bit in FMC_CTL register will be set, and the FMC_CTL register
will be locked, then it will generate a bus error.
The OBPG bit and OBER bit in FMC_CTL are also protected by FMC_OBKEY register. The
unlocking sequence includes two write operations, which are writing 0x45670123 and
0xCDEF89AB to FMC_OBKEY register, then hardware set the OBWEN bit in FMC_CTL
register to 1. The software can set OBWEN bit to 0 to protect the OBPG bit and OBER bit in
FMC_CTL register again.
2.3.4. Page erase
The FMC provides a page erase function which is used for initializing the contents of a main
flash memory page to a high state. Each page can be erased independently without affecting
the contents of other pages. The following steps show the access sequence of the register
for a page erase operation.
1. Unlock the FMC_CTL register if necessary.
2. Check the BUSY bit in FMC_STAT register to confirm that no flash memory operation is
in progress (BUSY equal to 0). Otherwise, wait until the operation has been finished.
3. Write the page address into the FMC_ADDR register.
4. Write the page erase command into PER bit in FMC_CTL register.
5. Send the page erase command to the FMC by setting the START bit in FMC_CTL
register.
6. Wait until all the operations have been completed by checking the value of the BUSY bit
in FMC_STAT register.
7. Read and verify the page by using a DBUS access if necessary.
When the operation is executed successfully, the ENDF in FMC_STAT register is set, at this
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