GigaDevice Semiconductor GD32F3x0 - Software Trigger Register (DAC_SWT)

GD32F3x0 User Manual
199
These bits specify the mode selection of the noise wave signal of DAC when external
trigger of DAC is enabled (DTEN=1).
00: Wave disabled
01: LFSR noise mode
1x: Triangle noise mode
5:3
DTSEL[2:0]
DAC trigger selection
These bits are only used if bit DTEN = 1 and select the external event used to trigger
DAC.
000: TIMER5 TRGO event
001: TIMER2 TRGO event
010: Reserved
011: TIMER14 TRGO event
100: TIMER1 TRGO event
101: Reserved
110: EXTI line 9
111: Software trigger
2
DTEN
DAC trigger enable
0: DAC trigger disabled
1: DAC trigger enabled
1
DBOFF
DAC output buffer turn off
0: DAC output buffer turns on to reduce the output impedance and improve the
driving capability.
1: DAC output buffer turns off
0
DEN
DAC enable
0: DAC disabled
1: DAC enabled
12.4.2. Software trigger register (DAC_SWT)
Address offset: 0x04
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SWTR
w
Bits
Fields
Descriptions