GigaDevice Semiconductor GD32F3x0 - Register Definition

GD32F3x0 User Manual
121
6.6. Register definition
EXTI base address: 0x4001 0400
6.6.1. Interrupt enable register (EXTI_INTEN)
Address offset: 0x00
Reset value: 0x0F94 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
INTEN27
INTEN26
INTEN25
INTEN24
INTEN23
INTEN22
INTEN21
INTEN20
INTEN19
INTEN18
INTEN17
INTEN16
rw
rw
rw
Rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTEN15
INTEN14
INTEN13
INTEN12
INTEN11
INTEN10
INTEN9
INTEN8
INTEN7
INTEN6
INTEN5
INTEN4
INTEN3
INTEN2
INTEN1
INTEN0
rw
rw
rw
rw
rw
rw
rw
Rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:28
Reserved
Must be kept at reset value
27: 0
INTENx
Interrupt enable bit x(x=0..27)
0: Interrupt from Linex is disabled
1: Interrupt from Linex is enabled
6.6.2. Event enable register (EXTI_EVEN)
Address offset: 0x04
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
EVEN27
EVEN26
EVEN25
EVEN24
EVEN23
EVEN22
EVEN21
EVEN20
EVEN19
EVEN18
EVEN17
EVEN16
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EVEN15
EVEN14
EVEN13
EVEN12
EVEN11
EVEN10
EVEN9
EVEN8
EVEN7
EVEN6
EVEN5
EVEN4
EVEN3
EVEN2
EVEN1
EVEN0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:28
Reserved
Must be kept at reset value
27: 0
EVENx
Event enable bit x(x=0..27)
0: Event from Linex is disabled