Quad-SPI mode operation sequence
The Quad-SPI mode is designed to control Quad-SPI Flash.
In order to enter Quad-SPI mode, the software should first verify that the TBE bit is set and
TRANS bit is cleared, then set QMOD bit in SPI_QCTL register. In Quad-SPI mode, BDEN,
BDOEN, CRCEN, CRCNT, CRCL, RO and LF in SPI_CTL0 register should be kept cleared
and FF16 should be set to ensure that SPI data size is 8-bit, MSTMOD should be set to
ensure that SPI is in master mode. SPIEN, PSC, CKPL and CKPH should be configured as
desired.
There are two operation modes in Quad-SPI mode: quad write and quad read, decided by
QRD bit in SPI_QCTL register.
Quad write operation
SPI works in quad write mode when QMOD is set and QRD is cleared in SPI_QCTL register.
In this mode, MOSI, MISO, IO2 and IO3 are all used as output pins. SPI begins to generate
clock on SCK line and transmit data on MOSI, MISO, IO2 and IO3 as soon as data is written
into SPI_DATA (TBE is cleared) and SPIEN is set. Once SPI starts transmission, it always
checks TBE status at the end of a frame and stops when condition is not met.
The operation flow for transmitting in quad mode:
1. Configure clock prescaler, clock polarity, phase, etc. in SPI_CTL0 and SPI_CTL1 based
on application requirements.
2. Set QMOD bit in SPI_QCTL register and then enable SPI by setting SPIEN in
SPI_CTL0.
3. Write a byte to SPI_DATA register and the TBE will be cleared.
4. Wait until TBE is set by hardware again before writing the next byte.
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