GigaDevice Semiconductor GD32F3x0 - Figure 18-2. USART Character Frame (8 Bits Data and 1 Stop Bit); Table 18-2. Configuration of Stop Bits

GD32F3x0 User Manual
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Figure 18-2. USART character frame (8 bits data and 1 stop bit)
Idle frame
Break frame
Stop
CLOCK
Data frame
Start
bit4 bit5 bit6 bit7bit0 bit1 bit2 bit3
Start
Start
Stop
Start
or parity
In transmission and reception, the number of stop bits can be configured by the STB[1:0] bits
in the USART_CTL1 register.
Table 18-2. Configuration of stop bits
STB[1:0]
stop bit length (bit)
usage description
00
1
Default value
01
0.5
Smartcard mode for receiving
10
2
Normal USART and single-wire modes
11
1.5
Smartcard mode for transmitting and receiving
In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART
frame.
The break frame structure is a number of low bits followed by the configured number of stop
bits. The transfer speed of a USART frame depends on the frequency of the UCLK, the
configuration of the baud rate generator and the oversampling mode.
18.3.2. Baud rate generation
The baud-rate divider is a 16-bit number which consists of a 12-bit integer and a 4-bit
fractional part. The number formed by these two values is used by the baud-rate generator to
determine the bit period. Having a fractional baud-rate divider allows the USART to generate
all the standard baud rates.
The baud-rate divider (USARTDIV) has the following relationship with the UCLK:
In case of oversampling by 16, the equation is:
USARTDIV=
UCLK
16×Baud Rate
(18-1)
In case of oversampling by 8, the equation is:
USARTDIV=
UCLK
8×Baud Rate
(18-2)
For example, when oversampled by 16:
1. Get USARTDIV by caculating the value of USART_BUAD:
If USART_BUAD=0x21D, then INTDIV=33 (0x21), FRADIV=13 (0xD).
USARTDIV=33+13/16=33.81.