GigaDevice Semiconductor GD32F3x0 - APB1 Enable Register (RCU_APB1 EN)

GD32F3x0 User Manual
92
16
TIMER14EN
TIMER14 timer clock enable
This bit is set and reset by software.
0: Disabled TIMER14 timer clock
1: Enabled TIMER14 timer clock
15
Reserved
Must be kept at reset value
14
USART0EN
USART0 clock enable
This bit is set and reset by software.
0: Disabled USART0 clock
1: Enabled USART0 clock
13
Reserved
Must be kept at reset value
12
SPI0EN
SPI0 clock enable
This bit is set and reset by software.
0: Disabled SPI0 clock
1: Enabled SPI0 clock
11
TIMER0EN
TIMER0 timer clock enable
This bit is set and reset by software.
0: Disabled TIMER0 timer clock
1: Enabled TIMER0 timer clock
10
Reserved
Must be kept at reset value
9
ADCEN
ADC interface clock enable
This bit is set and reset by software.
0: Disabled ADC interface clock
1: Enabled ADC interface clock
8:1
Reserved
Must be kept at reset value
0
CFGCMPEN
System configuration and comparator clock enable
This bit is set and reset by software.
0: Disabled System configuration and comparator clock
1: Enabled System configuration and comparator clock
4.3.8. APB1 enable register (RCU_APB1EN)
Address offset:0x1C
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CECEN
DACEN
PMUEN
Reserved
I2C1EN
I2C0EN
Reserved
USART1
EN
Reserved
rw
rw
rw
rw
rw
rw