GigaDevice Semiconductor GD32F3x0 - Table 9-3. DMA Requests for each Channel

GD32F3x0 User Manual
157
Table 9-3. DMA requests for each channel
Peripheral
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
ADC
ADC(1)
ADC(2)
●
●
●
●
●
SPI/I2S
●
SPI/I2S0_RX
SPI/I2S0_TX
SPI1_RX
SPI1_TX
●
●
USART
●
USART0_TX(1)
USART0_RX(1)
USART0_TX(2)
USART1_TX
USART0_RX(2)
USART1_RX
●
●
I
2
C
●
I2C0_TX
I2C0_RX
I2C1_TX
I2C1_RX
●
●
TIMER0
●
TIMER0_CH0
TIMER0_CH1
TIMER0_CH3
TIMER0_TRIG
TIMER0_COM
TIMER0_CH2
TIMER0_UP
●
●
TIMER1
TIMER1_CH2
TIMER1_UP
TIMER1_CH1
TIMER1_CH3
TIMER1_CH0
●
●
TIMER2
●
TIMER2_CH2
TIMER2_CH3
TIMER2_UP
TIMER2_CH0
TIMER2_TRIG
●
●
●
TIMER5/
DAC
●
●
TIMER5_UP
DAC
●
●
●
●
TIMER14
●
●
●
●
TIMER14_CH0
TIMER14_UP
TIMER14_TRIG
TIMER14_COM
TIMER14_CH1
●
●
TIMER15
●
●
TIMER15_CH0(1)
TIMER15_UP(1)
TIMER15_CH0(2)
TIMER15_UP(2)
●
●
●
TIMER16
TIMER16_CH0(1)
TIMER16_UP(1)
TIMER16_CH0(2)
TIMER16_UP(2)
●
●
●
●
●
1. When the corresponding remapping bit in the SYSCFG_CFGR0 register is cleared, the
request is mapped on the channel.
2. When the corresponding remapping bit in the SYSCFG_CFGR0 register is set, the
request is mapped on the channel.