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GigaDevice Semiconductor GD32F3x0 - Table 11-5. Maximum Output Results for N and M Combimations (Grayed Values Indicates Truncation)

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GD32F3x0 User Manual
181
Figure 11-12. Numerical example with 5-bits shift and rounding
2 A C D 6
Raw 20-bit
data
19 15 11 7 3 0
1 5 6 6
15 11 7 3 0
Final result after 5-bit shift
and rounding to nearest
Table 11-5. Maximum output results for N and M combimations (grayed values
indicates truncation) gives the data format for the various N and M combination, for a raw
conversion data equal to 0xFFF.
Table 11-5. Maximum output results for N and M combimations (grayed values
indicates truncation)
Oversa
mpling
ratio
Max
Raw
data
No-shift
OVSS=
0000
1-bit
shift
OVSS=
0001
2-bit
shift
OVSS=
0010
3-bit
shift
OVSS=
0011
4-bit
shift
OVSS=
0100
5-bit
shift
OVSS=
0101
6-bit
shift
OVSS=
0110
7-bit
shift
OVSS=
0111
8-bit
shift
OVSS=
1000
2x
0x1FFE
0x1FFE
0x0FFF
0x07FF
0x03FF
0x01FF
0x00FF
0x007F
0x003F
0x001F
4x
0x3FFC
0x3FFC
0x1FFE
0x0FFF
0x07FF
0x03FF
0x01FF
0x00FF
0x007F
0x003F
8x
0x7FF8
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x07FF
0x03FF
0x01FF
0x00FF
0x007F
16x
0xFFF0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x07FF
0x03FF
0x01FF
0x00FF
32x
0x1FFE0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x07FF
0x03FF
0x01FF
64x
0x3FFC0
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x07FF
0x03FF
128x
0x7FF80
0xFF80
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
0x07FF
256x
0xFFF00
0xFF00
0xFF80
0xFFC0
0xFFE0
0xFFF0
0x7FF8
0x3FFC
0x1FFE
0x0FFF
When compared to standard conversion mode, the conversion timings of oversampling
mode do not change, and the sampling time remains equal throughout the oversampling
sequence. New data is supplied every N conversions, and the equivalent delay is equal to:
N x t
ADC
= N x (t
SMPL
+ t
CONV
) (11-2)
Oversampling work with ADC modes
Most of the ADC work modes are available when oversampling is enabled.
Routine sequence.
ADC started by software or external triggers.
Single or scan, continuous or discontinuous operation modes.
Programmable sample time.
Analog watchdog.

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