GigaDevice Semiconductor GD32F3x0 - DAC 12-Bit Right-Aligned Data Holding Register(DAC_R12 DH); DAC 12-Bit Left-Aligned Data Holding Register(DAC_L12 DH)

GD32F3x0 User Manual
200
31:1
Reserved
Must be kept at reset value.
0
SWTR
DAC software trigger, cleared by hardware.
0: Software trigger disabled
1: Software trigger enabled
12.4.3. DAC 12-bit right-aligned data holding register(DAC_R12DH)
Address offset: 0x08
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DAC_DH[11:0]
rw
Bits
Fields
Descriptions
31:12
Reserved
Must be kept at reset value.
11:0
DAC_DH[11:0]
DAC 12-bit right-aligned data
These bits specify the data that is to be converted by DAC.
12.4.4. DAC 12-bit left-aligned data holding register(DAC_L12DH)
Address offset: 0x0C
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC_DH[11:0]
Reserved
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:4
DAC_DH[11:0]
DAC 12-bit left-aligned data
These bits specify the data that is to be converted by DAC.
3:0
Reserved
Must be kept at reset value.