GigaDevice Semiconductor GD32F3x0 - Register Definition

GD32F3x0 User Manual
50
2.4. Register definition
Base address: 0x4002 2000
2.4.1. Wait state register (FMC_WS)
Address offset: 0x00
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
WSCNT[2:0]
rw
Bits
Fields
Descriptions
31:3
Reserved
Must be kept at reset value
2:0
WSCNT[2:0]
Wait state counter register
These bits set and reset by software. The WSCNT valid when WSEN bit is set
000: 0 wait state added
001: 1 wait state added
010: 2 wait state added
011 ~ 111: Reserved
2.4.2. Unlock key register (FMC_KEY)
Address offset: 0x04
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEY[31:16]
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
KEY[15:0]
w
Bits
Fields
Descriptions
31:0
KEY[31:0]
FMC_CTL unlock registers
These bits are only be written by software
Write KEY [31:0] with key to unlock FMC_CTL register.