GigaDevice Semiconductor GD32F3x0 - Figure 21-7. Transmission Error Detection; Table 21-2. Error Handling Timing Parameter Table

GD32F3x0 User Manual
560
High
Impedence
Low Impedence
Ts
Logic
0
Logic
1
1.5ms 2.4ms
T1
0.6ms
T2 T5
T3 T4 T6 T7 T8
2.4ms
Legend:
Checking Window
BRE
BRE
SBPE
Nominal sample time 1.05 ms
LBPE
High
Impedence
Low Impedence
Table 21-2. Error Handling Timing Parameter Table
Symbol
RTOL
Time(ms)
Description
Ts
-
0ms
The bit start event.
T1
1
0.3ms
When indicating a logical 1, T1 as the earliest time for a low -
high transition.
0
0.4ms
T2
0
0.8ms
When indicating a logical 1, T2 as the latest time for a low - high
transition.
1
0.9ms
T3
-
0.85ms
The earliest time it is safe to sample the signal line to determine
its state.
T4
-
1.25ms
The latest time it is safe to sample the signal line to determine
its state.
T5
1
1.2ms
T5 as the earliest time that a device is allowed to return to a high
impedance state(logical 0).
0
1.3ms
T6
0
1.7ms
T6 as the latest time that a device is allowed to return to a high
impedance state(logical 0).
1
1.8ms
T7
1
1.85ms
T7 as the earliest time for the start of a following bit.
0
2.05ms
2.4ms
As a nominal data bit period.
T8
0
2.75ms
T8 as the latest time for the start of a following bit.
1
2.95ms
Transmission error detection(TERR)
The TERR is set when the initiator find low impedance on the CEC bus when it is
transmitting high impedance. TERR will also generate CEC interrupt if TERRIE=1.
When TERR asserted the transmission is aborted and the software can retry the
transmission.
TERR check window is depending on the different bit state of the frame shown as below:
Figure 21-7. Transmission error detection