GigaDevice Semiconductor GD32F3x0 - Control and Status Register (PMU_CS)

GD32F3x0 User Manual
67
1
STBMOD
Standby Mode
0: Enter the Deep-sleep mode when the Cortex
®
-M4 enters SLEEPDEEP mode
1: Enter the Standby mode when the Cortex
®
-M4 enters SLEEPDEEP mode
0
LDOLP
LDO Low Power Mode
0: The LDO operates normally during the Deep-sleep mode
1: The LDO is in low power mode during the Deep-sleep mode
Note: Some peripherals may work with the IRC8M clock in the Deep-sleep mode.
In this case, the LDO automatically switches from the low power mode to the
normal mode and remains in this mode until the peripheral stop working.
3.4.2. Control and status register (PMU_CS)
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
This register can be accessed by half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
LDRF[1:0]
HDSRF
HDRF
rc_w1
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LDOVSR
F
WUPEN6
WUPEN5
WUPEN4
Reserved
WUPEN1
WUPEN0
Reserved
LVDF
STBF
WUF
r
rw
rw
rw
rw
rw
r
r
r
Bits
Fields
Descriptions
31:20
Reserved
Must be kept at reset value.
19:18
LDRF[1:0]
Low-driver mode ready flag
These bits are set by hardware when enter Deep-sleep mode and the LDO in
Low-driver mode. These bits are cleared by software when write 11.
00: normal driver in Deep-sleep mode
01: Reserved
10: Reserved
11: Low-driver mode in Deep-sleep mode
17
HDSRF
High-driver switch ready flag
0: High-driver switch not ready
1: High-driver switch ready
16
HDRF
High-driver ready flag
0: High-driver not ready
1: High-driver ready
15
LDOVSRF
LDO voltage select ready flag
0: LDO voltage select not ready