GigaDevice Semiconductor GD32F3x0 - Page 66

GD32F3x0 User Manual
66
00: Reserved (LDO output voltage low mode)
01: LDO output voltage low mode
10: LDO output voltage mid mode
11: LDO output voltage high mode
13:12
Reserved
Must be kept at reset value.
11
LDNP
Low-driver mode when use normal power LDO
0: normal driver when use normal power LDO
1: Low-driver mode enabled when LDEN is 0b’11 and use normal power LDO
10
LDLP
Low-driver mode when use low power LDO.
0: normal driver when use low power LDO
1: Low-driver mode enabled when LDEN is 0b’11 and use low power LDO
9
Reserved
Must be kept at reset value.
8
BKPWEN
Backup Domain Write Enable
0: Disable write access to the registers in Backup domain
1: Enable write access to the registers in Backup domain
After reset, any write access to the registers in Backup domain is ignored. This bit
has to be set to enable write access to these registers.
7:5
LVDT[2:0]
Low Voltage Detector Threshold
000: 2.1V
001: 2.3V
010: 2.4V
011: 2.6V
100: 2.7V
101: 2.9V
110: 3.0V
111: 3.1V
4
LVDEN
Low Voltage Detector Enable
0: Disable Low Voltage Detector
1: Enable Low Voltage Detector
Note: When LVD_LOCK bit is set to 1 in the SYSCFG_CFG1 register, LVDEN and
LVDT[2:0] are read only.
3
STBRST
Standby Flag Reset
0: No effect
1: Reset the standby flag
This bit is always read as 0.
2
WURST
Wakeup Flag Reset
0: No effect
1: Reset the wakeup flag
This bit is always read as 0.