GigaDevice Semiconductor GD32F3x0 - Routine Data Register (ADC_RDATA); Oversampling Control Register (ADC_OVSAMPCTL)

GD32F3x0 User Manual
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Bits
Fields
Descriptions
31:30
Reserved
Must be kept at reset value.
29:25
RSQ5[4:0]
refer to RSQ0[4:0] description
24:20
RSQ4[4:0]
refer to RSQ0[4:0] description
19:15
RSQ3[4:0]
refer to RSQ0[4:0] description
14:10
RSQ2[4:0]
refer to RSQ0[4:0] description
9:5
RSQ1[4:0]
refer to RSQ0[4:0] description
4:0
RSQ0[4:0]
The channel number (0..18) are written to these bits to select a channel as the nth
conversion in the routine sequence.
11.5.11. Routine data register (ADC_RDATA)
Address offset: 0x4C
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDATA [15:0]
r
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
RDATA [15:0]
Routine channel data
These bits contain the conversion result from routine channel, which is read only.
11.5.12. Oversampling control register (ADC_OVSAMPCTL)
Address offset: 0x80
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
TOVS
OVSS [3:0]
OVSR [2:0]
Reserved
OVSEN