GigaDevice Semiconductor GD32F3x0 - Page 192

GD32F3x0 User Manual
192
rw
rw
rw
rw
Bits
Fields
Descriptions
31:10
Reserved
Must be kept at reset value.
9
TOVS
Triggered Oversampling
This bit is set and cleared by software.
0: All oversampled conversions for a channel are done consecutively after a trigger
1: Each conversion needs a trigger for a oversampled channel and the number of
triggers is determined by the oversampling ratio (OVSR [2:0]).
Note: The software allows this bit to be written only when ADCON = 0 (this ensures
that no conversion is in progress).
8:5
OVSS [3:0]
Oversampling shift
These bits are set and cleared by software.
0000: No shift
0001: Shift 1-bit
0010: Shift 2-bits
0011: Shift 3-bits
0100: Shift 4-bits
0101: Shift 5-bits
0110: Shift 6-bits
0111: Shift 7-bits
1000: Shift 8-bits
Other codes reserved
Note: The software allows this bit to be written only when ADCON = 0 (this ensures
that no conversion is in progress).
4:2
OVSR [2:0]
Oversampling ratio
These bits filed define the number of oversampling ratio.
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
111: 256x
Note: The software allows this bit to be written only when ADCON = 0 (this ensures
that no conversion is in progress).
1
Reserved
Must be kept at reset value.
0
OVSEN
Oversampling Enable
These bits are set and cleared by software.
0: Oversampling disabled