GigaDevice Semiconductor GD32F3x0 - Backup Registers (Rtc_Bkpx) (X = 0

GD32F3x0 User Manual
248
Bits
Fields
Descriptions
31:28
Reserved
Must be kept at reset value.
27:24
MSKSSC[3:0]
Mask control bit of SSC
0x0: Mask alarm sub second setting. The alarm asserts at every second time point
if all the rest alarm fields are matched.
0x1: SSC[0] is to be compared and all others are ignored
0x2: SSC[1:0] is to be compared and all others are ignored
0x3: SSC[2:0] is to be compared and all others are ignored
0x4: SSC[3:0] is to be compared and all others are ignored
0x5: SSC[4:0] is to be compared and all others are ignored
0x6: SSC[5:0] is to be compared and all others are ignored
0x7: SSC[6:0] is to be compared and all others are ignored
0x8: SSC[7:0] is to be compared and all others are ignored
0x9: SSC[8:0] is to be compared and all others are ignored
0xA: SSC[9:0] is to be compared and all others are ignored
0xB: SSC[10:0] is to be compared and all others are ignored
0xC: SSC[11:0] is to be compared and all others are ignored
0xD: SSC[12:0] is to be compared and all others are ignored
0xE: SSC[13:0] is to be compared and all others are ignored
0xF: SSC[14:0] is to be compared and all others are ignored
Note: The bit 15 of synchronous counter (SSC[15] in RTC_SS) is never compared.
23:15
Reserved
Must be kept at reset value.
14:0
SSC[14:0]
Alarm sub second value
This value is the alarm sub second value which is to be compared with
synchronous prescaler counter SSC. Bit number is controlled by MSKSSC bits.
15.4.16. Backup registers (RTC_BKPx) (x = 0..4)
Address offset: 0x50 + 4 * x (x = 0..4)
Backup domain reset: 0x0000 0000
System reset: no effect
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DATA[31:16]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[15:0]
rw
Bits
Fields
Descriptions
31:0
DATA[31:0]
Data
These registers can be written or read by software. The content remains valid even