GigaDevice Semiconductor GD32F3x0 - Figure 16-72. Timing Chart of up Counting Mode, Change Timerx_Car on the Go

GD32F3x0 User Manual
408
Figure 16-72. Timing chart of up counting mode, change TIMERx_CAR on the go
TIMER_CK
CEN
PSC_CLK
CNT_REG
94 95 96 97 98 99
0 1 2 3 4
5 6 7
Update event (UPE)
Update interrupt flag (UPIF)
Auto-reload register
120
99
change CAR Vaule
CNT_REG
113 114 115 116 117 118
119 120 0 1 2
98 99 0
Update event (UPE)
Update interrupt flag (UPIF)
Auto-reload register
120
99
change CAR Vaule
120 99
Auto-reload shadow register
...
Hardware set
Hardware set
Software clear
Hardware set
ARSE = 0
ARSE = 1
Update event (from overflow/underflow) rate configuration
The rate of update events generation (from overflow and underflow events) can be
configured by the TIMERx_CREP register. Counter repetition is used to generator update
event or updates the timer registers only after a given number (N+1) of cycles of the counter,
where N is CREP in TIMERx_CREP register. The repetition counter is decremented at each
counter overflow in up counting mode.
Setting the UPG bit in the TIMERx_SWEVG register will reload the content of CREP in
TIMERx_CREP register and generator an update event.