GD32F3x0 User Manual
61
Generally, digital circuits are powered by V
DD
, while most of analog circuits are powered by
V
DDA
. To improve the ADC and DAC conversion accuracy, the independent power supply
V
DDA
is implemented to achieve better performance of analog circuits. V
DDA
can be externally
connected to V
DD
through the external filtering circuit that avoids noise on V
DDA
, and V
SSA
should be connected to V
SS
through the specific circuit independently. Otherwise, if V
DDA
is
different from V
DD
, V
DDA
must always be higher, but the voltage difference should not exceed
0.3V.
To ensure a high accuracy on ADC and DAC, the ADC / DAC independent external reference
voltage should be connected to V
REF+
/ V
REF-
pins. According to the different packages, V
REF+
pin can be connected to V
DDA
pin, or external reference voltage which refers to Table 11-2.
ADC input pins definition and Table 12-1. DAC I/O description, V
REF-
pin must be
connected to V
SSA
pin. The V
REF+
pin is only available on no less than 100-pin packages, or
else the V
REF+
pin is not available and internally connected to V
DDA
. The V
REF-
pin is only
available on no less than 100-pin packages, or else the V
REF-
pin is not available and
internally connected to V
SSA
.
3.3.3. 1.2V power domain
The 1.2V power domain supplies for Cortex
®
-M4 logic, AHB / APB peripherals, the APB
interfaces for the Backup domain and the V
DD
/ V
DDA
domain, etc. Once the 1.2V is powered
up, the POR will generate a reset sequence on the 1.2V power domain. To enter the
expected power saving mode, the associated control bits must be configured. Then, once a
WFI (Wait for Interrupt) or WFE (Wait for Event) instruction is executed, the device will enter
an expected power saving mode which will be discussed in the following section.
High-driver mode
If the 1.2V power domain need to run with high frequency and open many functions
simultaneously, it is recommended to enter high-driver mode. The following steps are
needed when using high-driver mode.
IRC8M or HXTAL selected as system clock.
Set HDEN bit in PMU_CTL register to 1 to open high-driver mode.
Wait HDRF bit be set to 1 in PMU_CS register.
Set HDS bit in PMU_CTL register to 1 to switch LDO to high-driver mode.
Wait HDSRF bit be set to 1 in PMU_CS register. And enter high-driver mode.
Running the application at high frequency by PLL configurations.
The high-driver mode exit by resetting HDEN and HDS bits in PMU_CTL register after
IRC8M or HXTAL selected as system clock. The high-driver mode exit automatically when
exiting from Deep-sleep mode.
3.3.4. Power saving modes
After a system reset or a power reset, the GD32F3x0 MCU operates at full function and all
power domains are active. Users can achieve lower power consumption through slowing
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