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GigaDevice Semiconductor GD32F3x0 - Figure 16-11. Repetition Counter Timing Chart of down Counting Mode

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GD32F3x0 User Manual
261
Figure 16-11. Repetition counter timing chart of down counting mode
CEN
CNT_REG
3 2 1 0 99 98
.
1 0 99 98
.
1 0
Underflow
Overflow
TIMERx_CREP = 0x0
TIMER_CK
99
98
.
1 0 99
98
UPIF
TIMERx_CREP = 0x1
.
1 0
99
98
.
1 0 99
98
UPIF
UPIF
TIMERx_CREP = 0x2
PSC_CLK
Input capture and output compare channels
The advanced timer has four independent channels which can be used as capture inputs or
compare match outputs. Each channel is built around a channel capture compare register
including an input stage, channel controller and an output stage.
Channel input capture function
Channel input capture function allows the channel to perform measurements such as pulse
timing, frequency, period, duty cycle and so on. The input stage consists of a digital filter, a
channel polarity selection, edge detection and a channel prescaler. When a selected edge
occurs on the channel input, the current value of the counter is captured into the
TIMERx_CHxCV register, at the same time the CHxIF bit is set and the channel interrupt is
generated if enabled by CHxIE = 1.

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