GD32F3x0 User Manual
313
Counter center-aligned counting
In the center-aligned counting mode, the counter counts up from 0 to the counter-reload
value and then counts down to 0 alternatively. The TIMER module generates an overflow
event when the counter counts to the counter-reload value subtract 1 in the up-counting
mode and generates an underflow event when the counter counts to 1 in the down-counting
mode. The counting direction bit DIR in the TIMERx_CTL0 register is read-only and indicates
the counting direction when in the center-aligned mode.
Setting the UPG bit in the TIMERx_SWEVG register will initialize the counter value to 0
irrespective of whether the counter is counting up or down in the center-align counting mode
and generates an update event.
The UPIF bit in the TIMERx_SWEVG register can be set to 1 when an underflow event at
count-down (CAM in TIMERx_CTL0 is “2’b01”), an overflow event at count-up (CAM in
TIMERx_CTL0 is “2’b10”) or both of them occur (CAM in TIMERx_CTL0 is “2’b11”).
If the UPDIS bit in the TIMERx_CTL0 register is set, the update event is disabled.
When an update event occurs, all the shadow registers (counter autoreload register,
prescaler register) are updated.
Figure 16-36. Center-aligned counter timechart show some examples of the counter
behavior for different clock frequencies when TIMERx_CAR=0x99. TIMERx_PSC=0x0
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