EasyManua.ls Logo

GigaDevice Semiconductor GD32F3x0 - Page 314

Default Icon
665 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
GD32F3x0 User Manual
314
Figure 16-36. Center-aligned counter timechart
Hardware set
Software clear
CEN
PSC_CLK
CNT_REG
3 2 1 0 1 2
.
98 99 98
1 0
Underflow
Overflow
TIMERx_CTL0 CAM = 2'b11
TIMER_CK
1
2
.
98 99 98
97
UPIF
CHxIF
CHxIF
TIMERx_CTL0 CAM = 2'b10 (upcount only )
TIMERx_CTL0 CAM = 2'b10 (downcount only )
CHxIF
CHxCV=2
2 1
2
Input capture and output compare channels
The general level0 TIMER has four independent channels which can be used as capture
inputs or compare match outputs. Each channel is built around a channel capture compare
register including an input stage, channel controller and an output stage.
Channel input capture function
Channel input capture function allows the channel to perform measurements such as pulse
timing, frequency, period, duty cycle and so on. The input stage consists of a digital filter, a
channel polarity selection, edge detection and a channel prescaler. When a selected edge
occurs on the channel input, the current value of the counter is captured into the
TIMERx_CHxCV register, at the same time the CHxIF bit is set and the channel interrupt is
generated if enabled by CHxIE = 1.

Table of Contents

Related product manuals