1101: (CK_SYS / 128) selected
1110: (CK_SYS / 256) selected
1111: (CK_SYS / 512) selected
System clock switch status
Set and reset by hardware to indicate the clock source of system clock.
00: Select CK_IRC8M as the CK_SYS source
01: Select CK_HXTAL as the CK_SYS source
10: Select CK_PLL as the CK_SYS source
11: Reserved
System clock switch
Set by software to select the CK_SYS source. Because the change of CK_SYS
has inherent latency, software should read SCSS to confirm whether the switching
is complete or not. The switch will be forced to IRC8M when leaving Deep-sleep
and Standby mode or by HXTAL clock monitor when the HXTAL failure is detected
and the HXTAL is selected as the clock source of CK_SYS or PLL.
00: Select CK_IRC8M as the CK_SYS source
01: Select CK_HXTAL as the CK_SYS source
10: Select CK_PLL as the CK_SYS source
11: Reserved
4.3.3. Interrupt register (RCU_INT)
Address offset: 0x08
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
Must be kept at reset value
HXTAL Clock Stuck Interrupt Clear
Write 1 by software to reset the CKMIF flag.
0: Not reset CKMIF flag
1: Reset CKMIF flag
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