GigaDevice Semiconductor GD32F3x0 - Page 82

GD32F3x0 User Manual
82
Set and cleared by software to divide or not which is selected to PLL.
0: HXTAL or CK_IRC48M clock selected
1: (HXTAL or CK_IRC48M) / 2 clock selected
16
PLLSEL
PLL Clock Source Selection
Set and reset by software to control the PLL clock source.
0: (IRC8M / 2) clock selected as source clock of PLL
1: HXTAL or IRC48M(PLLPRESEL of RCU_CFG1 register) selected as source
clock of PLL
15:14
ADCPSC[1:0]
ADC clock prescaler selection
These bits and bit 31 of RCU_CFG2 are written by software to define the ADC
clock prescaler.Set and cleared by software.
000: (CK_APB2 / 2) selected
001: (CK_ APB2 / 4) selected
010: (CK_ APB2 / 6) selected
011: (CK_ APB2 / 8) selected
100: (CK_AHB / 3) selected
101: (CK_ AHB / 5) selected
110: (CK_ AHB / 7) selected
111: (CK_ AHB / 9) selected
13:11
APB2PSC[2:0]
APB2 prescaler selection
Set and reset by software to control the APB2 clock division ratio.
0xx: CK_AHB selected
100: (CK_AHB / 2) selected
101: (CK_AHB / 4) selected
110: (CK_AHB / 8) selected
111: (CK_AHB / 16) selected
10:8
APB1PSC[2:0]
APB1 prescaler selection
Set and reset by software to control the APB1 clock division ratio.
0xx: CK_AHB selected
100: (CK_AHB / 2) selected
101: (CK_AHB / 4) selected
110: (CK_AHB / 8) selected
111: (CK_AHB / 16) selected
7:4
AHBPSC[3:0]
AHB prescaler selection
Set and reset by software to control the AHB clock division ratio
0xxx: CK_SYS selected
1000: (CK_SYS / 2) selected
1001: (CK_SYS / 4) selected
1010: (CK_SYS / 8) selected
1011: (CK_SYS / 16) selected
1100: (CK_SYS / 64) selected