GigaDevice Semiconductor GD32F3x0 - Page 81

GD32F3x0 User Manual
81
21:18
PLLMF[3:0]
PLL multiply factor
These bits and bit 27 of RCU_CFG0 and bit 31 of RCU_CFG1 are written by
software to define the PLL multiplication factor.
000000: (PLL source clock x 2)
000001: (PLL source clock x 3)
000010: (PLL source clock x 4)
000011: (PLL source clock x 5)
000100: (PLL source clock x 6)
000101: (PLL source clock x 7)
000110: (PLL source clock x 8)
000111: (PLL source clock x 9)
001000: (PLL source clock x 10)
001001: (PLL source clock x 11)
001010: (PLL source clock x 12)
001011: (PLL source clock x 13)
001100: (PLL source clock x 14)
001101: (PLL source clock x 15)
001110: (PLL source clock x 16)
001111: (PLL source clock x 16)
010000: (PLL source clock x 17)
010001: (PLL source clock x 18)
010010: (PLL source clock x 19)
010011: (PLL source clock x 20)
010100: (PLL source clock x 21)
010101: (PLL source clock x 22)
010110: (PLL source clock x 23)
010111: (PLL source clock x 24)
011000: (PLL source clock x 25)
011001: (PLL source clock x 26)
011010: (PLL source clock x 27)
011011: (PLL source clock x 28)
011100: (PLL source clock x 29)
011101: (PLL source clock x 30)
011110: (PLL source clock x 31)
011111: (PLL source clock x 32)
100000: (PLL source clock x 33)
…
111110: (PLL source clock x 63)
111111: (PLL source clock x 64)
Note: The PLL output frequency must not exceed 108 MHz.
17
PLLPREDV
HXTAL or CK_IRC48M divider for PLL source clock selection. This bit is the same
bit as bit PREDV[0] from RCU_CFG1. Refer to RCU_CFG1 PREDV bits
description.