GigaDevice Semiconductor GD32F3x0 - Page 80

GD32F3x0 User Manual
80
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADCPSC[1:0]
APB2PSC[2:0]
APB1PSC[2:0]
AHBPSC[3:0]
SCSS[1:0]
SCS[1:0]
rw
rw
rw
rw
r
rw
Bits
Fields
Descriptions
31
PLLDV
The CK_PLL divide by 1 or 2 for CK_OUT
0: CK_PLL divide by 2 for CK_OUT
1: CK_PLL divide by 1 for CK_OUT
30:28
CKOUTDIV[2:0]
The CK_OUT divider which the CK_OUT frequency can be reduced
see bits 26:24 of RCU_CFG0 for CK_OUT.
000: The CK_OUT is divided by 1
001: The CK_OUT is divided by 2
010: The CK_OUT is divided by 4
011: The CK_OUT is divided by 8
100: The CK_OUT is divided by 16
101: The CK_OUT is divided by 32
110: The CK_OUT is divided by 64
111: The CK_OUT is divided by 128
27
PLLMF[4]
Bit 4 of PLLMF register
see bits 21:18 of RCU_CFG0.
26:24
CKOUTSEL[2:0]
CK_OUT Clock Source Selection
Set and reset by software.
000: No clock selected
001: Internal 28M RC oscillator clock selected
010: Internal 40K RC oscillator clock selected
011: External Low Speed oscillator clock selected
100: System clock selected
101: Internal 8MHz RC Oscillator clock selected
110: External High Speed oscillator clock selected
111: (CK_PLL / 2) or CK_PLL selected depend on PLLDV
23:22
USBFSPSC[1:0]
USBFS clock prescaler selection
These bits and bit 30 of RCU_CFG2 are written by software to define the USBFS
clock prescaler.Set and reset by software to control the USBFS clock prescaler
value. The USBFS clock must be 48MHz. These bits can’t be reset if the USBFS
clock is enabled.
000: (CK_PLL / 1.5) selected
001: CK_PLL selected
010: (CK_PLL / 2.5) selected
011: (CK_PLL / 2) selected
100: (CK_PLL / 3) selected
101/110/111: (CK_PLL / 3.5) selected