GD32F3x0 User Manual
210
14. Watchdog timer (WDGT)
The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system
failures due to software malfunctions. There are two watchdog timer peripherals in the chip:
free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a
combination of a high safety level, flexibility of use and timing accuracy. Both watchdog
timers are offered to resolve malfunctions of software.
The watchdog timer will generate a reset when the internal counter reaches a given value.
The watchdog timer counter can be stopped while the processor is in the debug mode.
14.1. Free watchdog timer (FWDGT)
14.1.1. Overview
The free watchdog timer (FWDGT) has free clock source (IRC40K). Thereupon the FWDGT
can operate even if the main clock fails. It’s suitable for the situation that requires an
independent environment and lower timing accuracy.
The free watchdog timer causes a reset when the internal down counter reaches 0. The
register write protection function in free watchdog can be enabled to prevent it from changing
the configuration unexpectedly.
14.1.2. Characteristics
Free-running 12-bit downcounter.
Reset when the downcounter reaches 0, if the watchdog is enabled.
Free clock source, FWDGT can operate even if the main clock fails such as in standby
and Deep-sleep modes.
Hardware free watchdog bit, automatically start the FWDGT at power on.
FWDGT debug mode, the FWDGT can stop or continue to work in debug mode.
14.1.3. Function overview
The free watchdog consists of an 8-stage prescaler and a 12-bit down-counter. Refer to the
Figure 14-1. Free watchdog timer block diagram for the functional block of the free
watchdog module.
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