The free watchdog is enabled by writing the value 0xCCCC in the control register
(FWDGT_CTL), and the counter starts counting down. When the counter reaches the value
0x000, a reset is generated.
The counter can be reloaded by writing the value 0xAAAA to the FWDGT_CTL register at
any time. The reload value comes from the FWDGT_RLD register. The software can prevent
the watchdog reset by reloading the counter before the counter reaches the value 0x000.
By setting the appropriate window in the FWDGT_WND register, the FWDGT can also work
as a window watchdog timer. A reset will occur if the reload operation is performed while the
counter is greater than the value stored in the window register (FWDGT_WND). The default
value of the FWDGT_WND is 0x0000 0FFF, so if it is not updated, the window option is
disabled. A reload operation is performed in order to reset the downcounter to the
FWDGT_RLD value and the prescaler counter to generate the next reload, as soon as the
window value is changed.
The free watchdog can automatically start at power on when the hardware free watchdog bit
in the device option bits is set. To avoid reset, the software should reload the counter before
the counter reaches 0x000.
The FWDGT_PSC register and the FWDGT_RLD register are written protected. Before
writing these registers, the software should write the value 0x5555 to the FWDGT_CTL
register. These registers will be protected again by writing any other value to the
FWDGT_CTL register. When an update operation of the prescaler register (FWDGT_PSC)
or the reload value register (FWDGT_RLD) is on going, the status bits in the FWDGT_STAT
register are set.
If the FWDGT_HOLD bit in DBG module is cleared, the FWDGT continues to work even the
Cortex
®
-M4 core halted (Debug mode). While the FWDGT stops in Debug mode if the
FWDGT_HOLD bit is set.
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