GigaDevice Semiconductor GD32F3x0 - Bit Clear Register (Gpiox_Bc, X=A; Port Bit Toggle Register (Gpiox_Tg, X=A

GD32F3x0 User Manual
142
These bits are set and cleared by software.
Refer to SEL8[3:0] description
3:0
SEL8[3:0]
Pin 8 alternate function selected
These bits are set and cleared by software.
0000: AF0 selected (reset value)
0001: AF1 selected
0010: AF2 selected
0011: AF3 selected
0100: AF4 selected (Port A,B only)
0101: AF5 selected (Port A,B only)
0110: AF6 selected (Port A,B only)
0111: AF7 selected (Port A,B only)
1000 ~ 1111: Reserved
7.4.11. Bit clear register (GPIOx_BC, x=A..D,F)
Address offset: 0x28
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:0
CRy
Port Clear bit y(y=0..15)
These bits are set and cleared by software.
0: No action on the corresponding OCTLy bit
1: Clear the corresponding OCTLy bit
7.4.12. Port bit toggle register (GPIOx_TG, x=A..D,F)
Address offset: 0x2C
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16