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GigaDevice Semiconductor GD32F3x0 - Figure 16-73. Repetition Counter Timing Chart of up Counting Mode

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GD32F3x0 User Manual
409
Figure 16-73. Repetition counter timing chart of up counting mode
CEN
CNT_REG
96 97 98 99 0 1
98 99 0 1
98 99
Underflow
Overflow
TIMERx_CREP = 0x0
TIMER_CK
0
1
98 99 0
1
UPIF
TIMERx_CREP = 0x1
98 99
0
1
98 99 0
1
UPIF
UPIF
TIMERx_CREP = 0x2
PSC_CLK
Input capture and output compare channels
The general level4 timer has one independent channels which can be used as capture inputs
or compare match outputs. Each channel is built around a channel capture compare register
including an input stage, channel controller and an output stage.
Channel input capture function
Capture mode allows the channel to perform measurements such as pulse timing, frequency,
period, duty cycle and so on. The input stage consists of a digital filter, a channel polarity
selection, edge detection and a channel prescaler. When a selected edge occurs on the
channel input, the current value of the counter is captured into the TIMERx_CHxCV register,
at the same time the CHxIF bit is set and the channel interrupt is generated if enabled by
CHxIE = 1.

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