GD32F3x0 User Manual
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11.4.2. Dual clock domain architecture
The ADC sub-module, with exception of the APB interface block, is feed by an ADC clock,
which can be asynchronous and independent from the APB clock.
Application can reduce PLCK frequency for low power operation while still keeping optimum
ADC performance.
Refer to RCU Section 4.2.1 for more information on generating this clock source.
11.4.3. ADCON enable
The ADC module is enabled or disabled by configuring the ADCON bit in the ADC_CTL1
register. The ADC module will keep in reset state if this bit is 0. For power saving, when this
bit is 0, the analog sub-module will enter power off mode. After ADC is enabled, you need
delay t
SU
time for sampling, the value of t
SU
please refer to the device datasheet.
11.4.4. Routine sequence
The channel management circuit can organize the sampling conversion channels into a
sequence: routine sequence. The routine sequence supports up to 16 channels, and each
channel is called routine channel.
The RL[3:0] bits in the ADC_RSQ0 register specify the total conversion sequence length.
The ADC_RSQ0~ADC_RSQ2 registers specify the selected channels of the routine
sequence.
11.4.5. Operation modes
Single operation mode
In the single operation mode, the ADC performs conversion on the channel specified in the
RSQ0[4:0] bits in ADC_RSQ2. When the ADCON is 1, the ADC samples and converts a
single channel, once the corresponding software trigger or external trigger is active.
Figure 11-2. Single operation mode
After conversion of a single routine channel, the conversion data will be stored in the
ADC_RDATA register, the EOC will be set. An interrupt will be generated if the EOCIE bit is
set.
Software procedure for single operation mode of a routine channel:
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