GigaDevice Semiconductor GD32F3x0 - Figure 11-4. Scan Operation Mode, Continuous Disable; Figure 11-5. Scan Operation Mode, Continuous Enable

GD32F3x0 User Manual
175
Scan operation mode
The scan operation mode will be enabled when SM bit in the ADC_CTL0 register is set. In
this mode, the ADC performs conversion on all channels with a specific routine sequence
specified in the ADC_RSQ0~ADC_RSQ2 registers. When the ADCON has been set high,
the ADC samples and converts specified channels one by one in routine sequence till the
end of sequence, once the corresponding software trigger or external trigger is active. The
conversion data will be stored in the ADC_RDATA register. After conversion of the routine
sequence, the EOC will be set. An interrupt will be generated if the EOCIE bit is set. The
DMA bit in ADC_CTL1 register must be set when the routine sequence works in scan mode.
After conversion of a routine sequence, the conversion can be restarted automatically if the
CTN bit in the ADC_CTL1 register is set.
Figure 11-4. Scan operation mode, continuous disable
CH2 CH1 CH5 CH7 CH11 CH16 CH2 CH1
· · ·
EOC
One circle of routine sequence, RL=7
Routine
trigger
CH12 CH17
Software procedure for scan operation mode on a routine sequence:
1. Set the SM bit in the ADC_CTL0 register and the DMA bit in the ADC_CTL1
register.
2. Configure ADC_RSQx and ADC_SAMPTx registers.
3. Configure ETERC and ETSRC bits in the ADC_CTL1 register if it is needed.
4. Prepare the DMA module to transfer data from the ADC_RDATA.
5. Set the SWRCST bit, or generate an external trigger for the routine sequence.
6. Wait the EOC flag to be set.
7. Clear the EOC flag by writing 0.
Figure 11-5. Scan operation mode, continuous enable
CH2 CH1 CH5 CH7 CH11 CH2 CH1
· ·
·
EOC
One circle of routine sequence, RL=4
Routine
trigger
CH5 CH7 CH11 CH2
Discontinuous operation mode
The discontinuous operation mode will be enabled when the DISRC bit in the ADC_CTL0
register is set. In this mode, the ADC performs a short sequence of n conversions (n does
not exceed 8) which is a part of the sequence of conversions selected in the
ADC_RSQ0~ADC_RSQ2 registers. The value of n is configured by the DISNUM[2:0] bits in