GigaDevice Semiconductor GD32F3x0 - Block Diagram; Figure 16-29. General Level 0 Timer Block Diagram

GD32F3x0 User Manual
307
16.2.3. Block diagram
Figure 16-29. General Level 0 timer block diagram provides details on the internal
configuration of the general level0 timer.
Figure 16-29. General Level 0 timer block diagram
=1
0
0
0
0
Input Logic
Synchronizer
&Filter
&Edge Detector
Edge selector
Prescaler
Trigger processor
Trigger Selector
&Counter
Quadrate Decoder
Counter
External Trigger
Input logic
Polarity selection
Edge detector
Prescaler
Filter
TIMERx
_CHxCV
Register
/Interrupt
Register set and update
Interrupt collector and
controller
APB BUS
CK_TIMER
CH0_IN
CH1_IN
CH2_IN
CH3_IN
CI0
ITI0
ITI1
ITI2
ITI3
ETI
CAR
Output Logic
generation of outputs signals in
compare
, PWM,and mixed modes
according to
initialization
, software
output mask
, and polarity control
CH0_O
DMA controller
TIMERx_TRGO
.
Interrupt
CH1_O
CH2_O
CH3_O
Update
Trigger
Cap/Com
DMA REQ
/ACK
TIMERx_CH0
TIMERx_CH1
TIMERx_CH2
TIMERx_CH3
TIMERx_TG
TIMERx_UP
PSC
PSC_CLK
TIMER_CK
req en/direct req set
ETIFP