GigaDevice Semiconductor GD32F3x0 - Address Register (FMC_ADDR)

GD32F3x0 User Manual
53
7
LK
FMC_CTL lock bit
This bit is cleared by hardware when right sequent written to FMC_KEY register.
This bit can be set by software.
6
START
Send erase command to FMC bit
This bit is set by software to send erase command to FMC. This bit is cleared by
hardware when the BUSY bit is cleared.
5
OBER
Option byte erase command bit
This bit is set or cleared by software.
0: No effect
1: Option byte erase command
4
OBPG
Option byte program command bit
This bit is set or cleared by software.
0: No effect
1: Option byte program command
3
Reserved
Must be kept at reset value
2
MER
Main flash mass erase command bit
This bit is set or cleared by software.
0: No effect
1: Main flash mass erase command
1
PER
Main flash page erase command bit
This bit is set or cleared by software.
0: No effect
1: Main flash page erase command
0
PG
Main flash page program command bit
This bit is set or cleared by software.
0: No effect
1: Main flash page program command
2.4.6. Address register (FMC_ADDR)
Address offset: 0x14
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR[31:16]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR[15:0]
rw