GigaDevice Semiconductor GD32F3x0 - Direct Memory Access Controller (DMA); Overview; Characteristics

GD32F3x0 User Manual
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9. Direct memory access controller (DMA)
9.1. Overview
The direct memory access (DMA) controller provides a hardware method of transferring data
between peripherals and/or memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Data can be quickly moved by DMA between
peripherals and memory as well as memory and memory without any CPU actions. There
are 7 channels in the DMA controller. Each channel is dedicated to manage memory access
requests from one or more peripherals. An arbiter is implemented inside to handle the priority
among DMA requests.
The system bus is shared by the DMA controller and the Cortex
®
-M4 core. When the DMA
and the CPU are targeting the same destination, the DMA access may stop the CPU access
to the system bus for some bus cycles. Round-robin scheduling is implemented in the bus
matrix to ensure at least half of the system bus bandwidth for the CPU.
9.2. Characteristics
 Programmable length of data to be transferred, max to 65536.
 7 channels and each channel are configurable.
 AHB and APB peripherals, FLASH, SRAM can be accessed as source and destination.
 Each channel is connected to fixed hardware DMA request.
 Software DMA channel priority (low, medium, high, ultra high) and hardware DMA
channel priority (DMA channel 0 has the highest priority and DMA channel 6 has the
lowest priority).
 Support independent 8, 16, 32-bit memory and peripheral transfer.
 Support independent fixed and increasing address generation algorithm of memory and
peripheral.
 Support circular transfer mode.
 Support peripheral to memory, memory to peripheral, and memory to memory transfers.
 One separate interrupt per channel with three types of event flags.
 Support interrupt enable and clear.