GigaDevice Semiconductor GD32F3x0 - High Resolution Frequency Compensation Register (RTC_HRFC)

GD32F3x0 User Manual
244
Backup domain reset: 0x0000 0000
System reset: no effect
This register will record the calendar date when TSF is set to 1.
Reset TSF bit will also clear this register.
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSC[15:0]
r
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
SSC[15:0]
Sub second value
This value is the counter value of synchronous prescaler when TSF is set to 1.
15.4.13. High resolution frequency compensation register (RTC_HRFC)
Address offset: 0x3C
Backup domain reset: 0x0000 0000
System Reset: no effect
This register is write protected.
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FREQI
CWND8
CWND16
Reserved
CMSK[8:0]
rw
rw
rw
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15
FREQI
Increase RTC frequency by 488.5PPM
0: No effect
1: One RTCCLK pulse is inserted every 2
11
pulses.
This bit should be used in conjunction with CMSK bit. If the input clock frequency is
32.768KHz, the number of RTCCLK pulses added during 32s calibration window is
(512 * FREQI) - CMSK
14
CWND8
Frequency compensation window 8 second selected
0: No effect
1: Calibration window is 8 second