GigaDevice Semiconductor GD32F3x0 - Register Definition

GD32F3x0 User Manual
65
3.4. Register definition
PMU base address: 0x4000 7000
3.4.1. Control register (PMU_CTL)
Address offset: 0x00
Reset value: 0x0000 C000 (reset by wakeup from Standby mode)
This register can be accessed by half-word (16-bit) or word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
LDEN[1:0]
HDS
HDEN
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LDOVS[1:0]
Reserved
LDNP
LDLP
Reserved
BKPWEN
LVDT[2:0]
LVDEN
STBRST
WURST
STBMOD
LDOLP
rs
rw
rw
rw
rw
rw
rc_w1
rc_w1
rw
rw
Bits
Fields
Descriptions
31:20
Reserved
Must be kept at reset value.
19:18
LDEN[1:0]
Low-driver mode enable in Deep-sleep mode
00: Low-driver mode disable in Deep-sleep mode
01: Reserved
10: Reserved
11: Low-driver mode enable in Deep-sleep mode
17
HDS
High-driver mode switch
Set this bit by software only when HDRF flag is set and IRC8M or HXTAL used as
system clock. After this bit is set, the system enters High-driver mode. This bit can
be cleared by software. And cleared by hardware when exit from Deep-sleep mode
or when the HDEN bit is clear.
0: No High-driver mode switch
1: High-driver mode switch
16
HDEN
High-driver mode enable
This bit is set by software only when IRC8M or HXTAL used as system clock. This
bit is cleared by software or by hardware when exit from Deep-sleep mode.
0: High-driver mode disable
1: High-driver mode enable
15:14
LDOVS[1:0]
LDO output voltage select
These bits are set by software when the main PLL closed. And the LDO output
voltage selected by LDOVS bits takes effect when the main PLL enabled. If the
main PLL closed, the LDO output voltage low mode selected (value of this bit filed
not changed).