GigaDevice Semiconductor GD32F3x0 - Register Definition

GD32F3x0 User Manual
110
5.4. Register definition
CTC base address: 0x4000 C800
5.4.1. Control register 0 (CTC_CTL0)
Address offset: 0x00
Reset value: 0x0000 2000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
TRIMVALUE[5:0]
SWREF
PUL
AUTO
TRIM
CNTEN
Reserved
EREFIE
ERRIE
CKWARN
IE
CKOKIE
rw
w
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:14
Reserved
Must be kept at reset value.
13:8
TRIMVALUE[5:0]
IRC48M trim value
When AUTOTRIM in CTC_CTL0 register is 0, these bits are set and cleared by
software. This mode used to software calibration.
When AUTOTRIM in CTC_CTL0 register is 1, these bits are read only. The value
automatically modified by hardware. This mode used to hardware trim.
The middle value is 32. When increase 1, the IRC48M clock frequency add around
57KHz. When decrease 1, the IRC48M clock frequency sub around 57KHz.
7
SWREFPUL
Software reference source sync pulse
This bit is set by software, and generates a reference sync pulse to CTC counter.
This bit is cleared by hardware automatically and read as 0.
0: No effect
1: generates a software reference source sync pulse
6
AUTOTRIM
Hardware automatically trim mode
This bit is set and cleared by software. When this bit is set, the hardware automatic
trim enabled, the TRIMVALUE bits in CTC_CTL0 register are modified by
hardware automatically, until the frequency of IRC48M clock is close to 48MHz.
0: Hardware automatic trim disabled
1: Hardware automatic trim enabled
5
CNTEN
CTC counter enable
This bit is set and cleared by software. This bit used to enable or disable the CTC
trim counter. When this bit is set, the CTC_CTL1 register cannot be modified.
0: CTC trim counter disabled