GigaDevice Semiconductor GD32F3x0 - Prescaler Register (RTC_PSC); Alarm 0 Time and Date Register (RTC_ALRM0 TD)

GD32F3x0 User Manual
239
Set by hardware if the year field of calendar date register is not the default value 0.
0: Calendar has not been initialized
1: Calendar has been initialized
3
SOPF
Shift function operation pending flag
0: No shift operation is pending
1: Shift function operation is pending
2:1
Reserved
Must be kept at reset value.
0
ALRM0WF
Alarm 0 configuration can be write flag
Set by hardware if alarm register can be written after ALRM0EN bit has reset.
0: Alarm registers programming is not allowed
1: Alarm registers programming is allowed
15.4.5. Prescaler register (RTC_PSC)
Address offset: 0x10
System reset: not effected
Backup domain reset value: 0x007F 00FF
This register is write protected and can only be written in initialization state.
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
FACTOR_A[6:0]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
FACTOR_S[14:0]
rw
Bits
Fields
Descriptions
31:23
Reserved
Must be kept at reset value.
22:16
FACTOR_A[6:0]
Asynchronous prescaler factor
ck_apre frequency = RTCCLK frequency/(FACTOR_A+1)
15
Reserved
Must be kept at reset value.
14:0
FACTOR_S[14:0]
Synchronous prescaler factor
ck_spre frequency = ck_apre frequency/(FACTOR_S+1)
15.4.6. Alarm 0 time and date register (RTC_ALRM0TD)
Address offset: 0x1C
System reset: not effect
Backup domain reset value: 0x0000 0000
This register is write protected and can only be written in initialization state.