GigaDevice Semiconductor GD32F3x0 - AHB Reset Register (RCU_AHBRST)

GD32F3x0 User Manual
97
1: Power reset generated
26
EPRSTF
External PIN reset flag
Set by hardware when an External PIN generated.
Reset by writing 1 to the RSTFC bit.
0: No External PIN reset generated
1: External PIN reset generated
25
OBLRSTF
Option byte loader reset flag
Set by hardware when an option byte loader generated.
Reset by writing 1 to the RSTFC bit.
0: No Option byte loader reset generated
1: Option byte loader reset generated
24
RSTFC
Reset flag clear
This bit is set by software to clear all reset flags.
0: Not clear reset flags
1: Clear reset flags
23
V12RSTF
V12 domain Power reset flag
Set by hardware when a V12 domain Power reset generated.
Reset by writing 1 to the RSTFC bit.
0: No V12 domain Power reset generated
1: V12 domain Power reset generated
22:2
Reserved
Must be kept at reset value
1
IRC40KSTB
IRC40K stabilization
Set by hardware to indicate if the IRC40K output clock is stable and ready for use.
0: IRC40K is not stable
1: IRC40K is stable
0
IRC40KEN
IRC40K enable
Set and reset by software.
0: Disable IRC40K
1: Enable IRC40K
4.3.11. AHB reset register (RCU_AHBRST)
Address offset: 0x28
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
TSIRST
Reserved
PFRST
Reserved
PDRST
PCRST
PBRST
PARST
Reserved
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0