GigaDevice Semiconductor GD32F3x0 - Function Overview; Figure 16-30. Timing Chart of Internal Clock Divided by 1

GD32F3x0 User Manual
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16.2.4. Function overview
Clock source configuration
The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an
alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]).
 SMC [2:0] == 3’b000. Internal timer clock CK_TIMER which is from module RCU.
The default internal clock source is the CK_TIMER used to drive the counter prescaler when
the SMC [2:0] == 3’b000. When the CEN is set, the CK_TIMER will be divided by PSC value
to generate PSC_CLK.
In this mode, the TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER
which is from RCU.
If the SMC [2:0] in the TIMERx_SMCFG register are setting to an available value including
0x1, 0x2, 0x3 and 0x7, the prescaler is clocked by other clock sources selected by the TRGS
[2:0] in the TIMERx_SMCFG register and described as follows. When the SMC [2:0] bits are
set to 0x4, 0x5 or 0x6, the internal clock CK_TIMER is the counter prescaler driving clock
source.
Figure 16-30. Timing chart of internal clock divided by 1
CK_TIMER
CEN
PSC_CLK = TIMER_CK
CNT_REG
Reload Pulse
17 18 19 20 21 22
update event
generate(UPG)
23 00 01 02 03 04 05 06
07
Update event (UPE)
 SMC [2:0] == 3’b111(external clock mode 0). External input pin source
The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising
or falling edge on the external pin TIMERx_CH0/TIMERx_CH1. This mode can be selected
by setting SMC [2:0] to 0x7 and the TRGS [2:0] to 0x4, 0x5 or 0x6.
And, the counter prescaler can also be driven by rising edge on the internal trigger input pin
ITI0/1/2/3. This mode can be selected by setting SMC [2:0] to 0x7 and the TRGS [2:0] to 0x0,