GigaDevice Semiconductor GD32F3x0 - Table 9-1. DMA Transfer Operation

GD32F3x0 User Manual
151
Table 9-1. DMA transfer operation
Transfer size
Transfer operations
Source
Destination
Source
Destination
32 bits
32 bits
1: Read B3B2B1B0[31:0] @0x0
2: Read B7B6B5B4[31:0] @0x4
3: Read BBBAB9B8[31:0] @0x8
4: Read BFBEBDBC[31:0] @0xC
1: Write B3B2B1B0[31:0] @0x0
2: Write B7B6B5B4[31:0] @0x4
3: Write BBBAB9B8[31:0] @0x8
4: Write BFBEBDBC[31:0] @0xC
32 bits
16 bits
1: Read B3B2B1B0[31:0] @0x0
2: Read B7B6B5B4[31:0] @0x4
3: Read BBBAB9B8[31:0] @0x8
4: Read BFBEBDBC[31:0] @0xC
1: Write B1B0[15:0] @0x0
2: Write B5B4[15:0] @0x2
3: Write B9B8[15:0] @0x4
4: Write BDBC[15:0] @0x6
32 bits
8 bits
1: Read B3B2B1B0[31:0] @0x0
2: Read B7B6B5B4[31:0] @0x4
3: Read BBBAB9B8[31:0] @0x8
4: Read BFBEBDBC[31:0] @0xC
1: Write B0[7:0] @0x0
2: Write B4[7:0] @0x1
3: Write B8[7:0] @0x2
4: Write BC[7:0] @0x3
16 bits
32 bits
1: Read B1B0[15:0] @0x0
2: Read B3B2[15:0] @0x2
3: Read B5B4[15:0] @0x4
4: Read B7B6[15:0] @0x6
1: Write 0000B1B0[31:0] @0x0
2: Write 0000B3B2[31:0] @0x4
3: Write 0000B5B4[31:0] @0x8
4: Write 0000B7B6[31:0] @0xC
16 bits
16 bits
1: Read B1B0[15:0] @0x0
2: Read B3B2[15:0] @0x2
3: Read B5B4[15:0] @0x4
4: Read B7B6[15:0] @0x6
1: Write B1B0[15:0] @0x0
2: Write B3B2[15:0] @0x2
3: Write B5B4[15:0] @0x4
4: Write B7B6[15:0] @0x6
16 bits
8 bits
1: Read B1B0[15:0] @0x0
2: Read B3B2[15:0] @0x2
3: Read B5B4[15:0] @0x4
4: Read B7B6[15:0] @0x6
1: Write B0[7:0] @0x0
2: Write B2[7:0] @0x1
3: Write B4[7:0] @0x2
4: Write B6[7:0] @0x3
8 bits
32 bits
1: Read B0[7:0] @0x0
2: Read B1[7:0] @0x1
3: Read B2[7:0] @0x2
4: Read B3[7:0] @0x3
1: Write 000000B0[31:0] @0x0
2: Write 000000B1[31:0] @0x4
3: Write 000000B2[31:0] @0x8
4: Write 000000B3[31:0] @0xC
8 bits
16 bits
1: Read B0[7:0] @0x0
2: Read B1[7:0] @0x1
3: Read B2[7:0] @0x2
4: Read B3[7:0] @0x3
1, Write 00B0[15:0] @0x0
2, Write 00B1[15:0] @0x2
3, Write 00B2[15:0] @0x4
4, Write 00B3[15:0] @0x6
8 bits
8 bits
1: Read B0[7:0] @0x0
2: Read B1[7:0] @0x1
3: Read B2[7:0] @0x2
4: Read B3[7:0] @0x3
1, Write B0[7:0] @0x0
2, Write B1[7:0] @0x1
3, Write B2[7:0] @0x2
4, Write B3[7:0] @0x3
The CNT bits in the DMA_CHxCNT register control how many data to be transmitted on the
channel and must be configured before enable the CHEN bit in the register. During the
transmission, the CNT bits indicate the remaining number of data items to be transferred.